The invention generally relates to control of instructions to a pipelined processor to efficiently limit power dissipation.
As used herein, xe2x80x9cinstructionsxe2x80x9d denote basic processor commands and other operations such as floating point operations. The following patents provide useful background for the invention, and are thus incorporated herein by reference: U.S. Pat. No. 5,938,755; U.S. Pat. No. 5,903,768; U.S. Pat. No. 5,898,235; U.S. Pat. No. 5,884,061; U.S. Pat. No. 5,751,984; U.S. Pat. No. 5,684,422; U.S. Pat. No. 5,557,531; U.S. Pat. No. 5,521,834; and U.S. Pat. No. 5,452,215;
Modern processors, like the PA-8000 microprocessor by Hewlett-Packard, use xe2x80x9cpipeliningxe2x80x9d to increase throughput at relatively low cost. Pipelining is a technique whereby the processor begins executing a second instruction before the first instruction is completed. Specifically, a pipelined processor partitions a process with xe2x80x9cmxe2x80x9d steps into xe2x80x9cmxe2x80x9d hardware stages separated by registers, which hold intermediate results. Each hardware stage thus has a stage execution circuit that performs the actual step or operation. One pipelined stage has one step in the process, and stages are connected in the order that the steps are performed. By permitting each of the xe2x80x9cmxe2x80x9d stages to operate concurrently, the pipelined process can substantially operate at xe2x80x9cmxe2x80x9d times the rate of a processor without pipelining. When any stage completes its operation, the result is passed to the next stage; and final results emerge at the end of the pipeline.
Pipelines are used to accelerate execution by operating on multiple computer instructions at once. FIG. 1 shows relevant structure within one illustrative prior art pipelined processor 10; and FIG. 2 shows an exemplary six-stage pipeline 20. Consistent with later-generation processors, processor 10 issues and retires more than a single instruction 22 per clock cycle, as illustrated in FIG. 2. In the first stage, the fetch (F) stage, processor 10 tells its cache 12 which instruction 22 to next put into register pipeline 14, containing separate register columns 14a-14f and stage execution circuits 20a-20e. Pipeline stages are separated by register columns 14a-f, each holding intermediate results for respective stages of the pipeline. The many outputs of register pipeline 14 are illustratively shown as transferred to a results section 16 within processor 10 for use in further operations.
For illustrative purposes, register columns 14a-f are shown with only three registers each; while the typical length of register columns 14a-14f has many more distinct registers. A particular pipeline process transpires across a particular row of register columns 14a-14f, such as the row of registers 15b. Stage execution circuits 20a-e execute the step or operation between respective register columns 14a-f. Each stage execution circuit 20 dissipates heat associated with the step or instruction being processed at that stage. Certain steps or instructions such as floating point operations dissipate more heat in circuits 20 than other steps or instructions in circuits 20.
The next stage after the F stage is the instruction decode (ID) stage, which might for example indicate an xe2x80x9caddxe2x80x9d or xe2x80x9csubtractxe2x80x9d or floating point (xe2x80x9cFPxe2x80x9d) calculation. The ID stage also starts to acquire the operand values from the appropriate register columns 14a-14e. 
Instructions are executed at the EX stage, here shown with two separate stages EX1 and EX2. Associated stage execution circuits 20c, 20d serve to process operations associated with these stages.
The memory stage (M) corresponds to a memory operation, if any; and the write stage (W) operates to write the result or float value at the sixth stage of the register pipeline 14. Results that emerge from register pipeline 14 are available to processor 10, illustratively, at result section 16.
Note that as shown in FIG. 2, two instructions 22 are clocked simultaneously for a given cycle. Thus, for example, the first two instructions 22 start at cycle 1 and complete simultaneously at cycle 6.
Those skilled in the art should appreciate that other forms of pipeline processing are known. For example, Hewlett-Packard""s PA-8000 processor has a two-level process, with one pipeline for instructions and a separate pipeline for floating point operations. Furthermore, the number of stages in a pipeline also varies. However, the maximum throughput of a single pipeline process is one instruction per cycle.
The afore-mentioned processors are typically at the heart of all personal computers, work stations and servers, i.e., computing xe2x80x9csystemsxe2x80x9d. Often, it is desirable to have more than one such processor within a single system. However, one difficulty with adding additional processors within computing systems is in compensating for power dissipation: pipelined processors generate heat, particularly within stage execution circuits 20 and register columns 14a-14f, FIG. 1; and this heat must be dissipated by the system""s cooling capabilities or the processor will fail. In the prior art, power dissipation in a pipelined processor is based upon the instantaneous dissipation of specific instructions and pipeline length integrated over time. However, the clock frequency and pipeline lengths are such that instantaneous power is not a good indicator of average power dissipation; and yet this calculated average power dissipation is used to determine the cooling requirements of the prior art system. Accordingly, this calculated average power is essentially a xe2x80x9cworst casexe2x80x9d power evaluation (i.e., an estimate based on maximal utilization of execution circuit resources) that unnecessarily (a) limits the numbers of processors which can be installed within a system or (b) over-specifies the cooling requirements of a system, adding cost, weight and unnecessary structure to a system. Other prior art methods for controlling pipeline processor power dissipation are also problematic. By way of example, control based on current pipeline snapshot is too reactive for the entire computing system. Control based on extended pipeline information requires significant additional hardware.
The prior art is also familiar with thermal sensors on die, used to monitor heat dissipation; however such sensors are complex and difficult to use in meaningful calculations.
It is, therefore, one object of the invention to provide a pipelined processor which variably dissipates processor power according to the actual processing needs of the computing system. Another object of the invention is to provide methods of controlling power dissipation of a pipelined microprocessing system in a manner that is correlated to the types of operations under process. Still another object of the invention is to provide a method of throttling instructions to a pipeline within a processor in a manner functionally related to the physical heat generated by the processor. These and other objects will become apparent in the description that follows.
The invention solves the afore-mentioned problems of controlling power dissipation by stalling high power instructions through the pipeline, and with minimal performance impact. In particular, one aspect of the invention provides a pipelined processor with a power dissipation controller that stalls high power instructions in order to control the processor""s average power dissipation. In a preferred aspect, the controller is modeled after a capacitive system with a constant output rate and a controlled input rate. The output rate represents the steady state power dissipation; while the input rate is controlled based upon the current capacity, representing thermal response. At start-up, the capacity is zero. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. Stalling of instructions occurs when the capacity exceeds a selected threshold; The invention of this aspect is thus based on a model of a current source feeding a capacitor in parallel with a resistor: the current source models the input rate and is controlled by the voltage across the capacitor, with the resistor modeling the output rate. Those skilled in the art should appreciate that the invention simplifies this model in actual implementation due to complexity and cost.
More particularly, in the preferred aspect of the invention, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit. This stall effectively creates a xe2x80x9cholexe2x80x9d at that pipeline stage, thus temporarily reducing power dissipation. The invention thus takes advantage of the fact that the presence of an instruction at any stage execution circuit dissipates power and that the absence (i.e., a xe2x80x9cholexe2x80x9d) of an instruction at any stage dissipates less power. By controlling where and when a hole occurs within the pipeline, the overall power dissipation of the processor is controlled. Technically, the power dissipation within the stage processing circuits is related to the charging and discharging of electrical nodes associated with the stage execution circuits; and the number of nodes that charge or discharge are reduced with an absence of a valid instruction. The invention of one aspect thus injects a low power bit (xe2x80x9clp-bitxe2x80x9d) at the desired stage execution circuit to reduce the power dissipation associated therewith.
There are several advantages of the invention. Unlike the prior art, code sequences with bursts of high powered instructions followed by sequences of low power instructions may not be throttled at all. If however the sequence of high power instruction is long, these will be throttled at a preset rate; and thus power control over a long period more closely matches the computing system""s actual power dissipation needs. Other advantages are also apparent with the invention:
Throttling takes into account the effects of prior executed high power instructions; and thus throttling occurs only when necessary and with minimal performance impact on bursting sequences.
Few resources are needed to implement the invention in hardware; and the user further has a choice to increase or decrease the constants used in feedback with the throttling effects.
Power control more closely matches the thermal response time of the computing system, with a response time many orders of magnitude longer than the pipeline length.
By way of example, consider the operation of the invention with a floating point operation. Floating point operations generate relatively large amounts of power and yet are, in effect, relatively non-critical for typical application software. Accordingly, the invention of one aspect tends to degrade the importance of floating point operations to reduce the number of watts generated by each processor, thereby permitting more processors for a given cooling capacity. The prior art does not operate in such a manner, and rather designs its computing systems to dissipate xe2x80x9cworst casexe2x80x9d processor-generated power, limiting the number of possible processors that can exist for a given cooling capacity.
In one aspect, the invention provides a method for controlling maximum average power dissipation in a pipelined processor, the processor of the type which processes instructions through pipelined stages, including the steps of: determining a first power dissipation generated by issued instructions; determining a capacity as the first power dissipation subtracted by a bleed rate; comparing the capacity to a predetermined threshold; and stalling instructions at a select stage in the pipelined stages when the capacity exceeds the threshold.
In another aspect, the step of determining a first power dissipation can include multiplying the issued instructions by an issue weight, corresponding to relative power dissipation.
The methods of the invention can also include the step of estimating the issue weight as a function of instruction type. Preferably, the issue weight is greater for instructions which dissipate greater energy within the processor.
In another aspect, the methods of the invention include the step of writing one or more system constants into processor registers prior to the step of determining the first power dissipation, the constants including bleed rate, issue weight, and threshold. These constants preferably provide for system operation with power dissipation controlled to a maximum average power dissipation rate relative to a throttled instruction input rate.
In yet another aspect, the method includes the step of resetting capacity to zero (or any other desired value) prior to processing instructions through the processor.
In another aspect, the step of stalling includes the step of asserting a lp-bit to a stage execution circuit within the processor. In subsequent cycles, the lp-bit is moved to a next stage execution circuit within the pipeline stages.
Alternatively, the method changes a first stage execution circuit to a low power state; and this method step can include the steps of (a) changing the first stage execution circuit out of a lower power state and (b) changing a second stage execution circuit to a low power state, where the second stage execution circuit is an adjacent downstream stage from the first stage execution circuit in the pipeline stages.
In still another aspect, the invention provides a pipelines processor with a register pipeline to process instructions through pipeline stages. The register pipeline has (a) a plurality of registers holding intermediate results between stages and (b) a plurality of stage execution circuits for executing instructions at associated stages. A power dissipation controller changes one or more stage execution circuits to a low power state and stall earlier instructions through the pipeline stages containing the stage execution circuits.
In another aspect, the power dissipation controller performs as a capacitive feedback to provide a maximum average power dissipation rate and a throttled instruction input rate. Register memory stores one or more system constants to provide the capacitive feedback according to internal logic. Preferably, the logic compares an internal threshold to a system capacity, computed as the number of issued instructions multiplied by respective issue weights and subtracted by a bleed rate; and the controller thereafter implements a low power state when the capacity exceeds the threshold.
In one aspect, the power dissipation controller controls maximum average power dissipated by the processor in a time frame that is greater than the pipeline length. In another aspect, the time frame is at least 10{circumflex over ( )}5 greater than the pipeline length.
The invention is next described further in connection with preferred embodiments, and it will become apparent that various additions, subtractions, and modifications can be made by those skilled in the art without departing from the scope of the invention.